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Researcher in framework for FPGA benchmarking of quantized neural networks - TIMA

Grenoble INP - Institute of Engineering | Grenoble, Rhone Alpes | France | 18 days ago

- Experience with RTL languages (Verilog or VHDL), VHDL would be a plus - Proficiency with English language is highly recommended - Proficiency with French language would be a plus - Interest in technologies

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