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research expertise in RISC-V architecture, processor microarchitecture, and AI accelerators. Experience with ASIC design methodologies and open-source IC design and EDA tools. Proven experience in digital
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. Strong research expertise in RISC-V architecture, processor microarchitecture, and AI accelerators. Experience with ASIC design methodologies and open-source IC design and EDA tools. Proven experience in
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electronics for sensor readout systems, including ASIC and SoC design and verification. Strong experience in hardware–firmware co-design for data acquisition and processing pipelines, including FPGA-based
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ASCON accelerator within the RISC-V CVA6 core. Investigate and implement RISC-V ISA extensions or custom instructions to support cryptographic operations. Execute the full ASIC design flow using open
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project team at INESC-ID is working on the development of specific components for the OpenSSD-V platform, focusing on hardware/software co-design and circuit synthesis for ASIC/FPGA. The objective
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satellite laboratories at the University of California at Berkeley (USA), Toyota Central R&D Lab., and ISAS at the Japanese space agency JAXA. These programs are designed to bridge quantum technologies with