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- Experience with RTL languages (Verilog or VHDL), VHDL would be a plus - Proficiency with English language is highly recommended - Proficiency with French language would be a plus - Interest in technologies
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design processes from RTL to GDSII ideally, experience in using Design-Flow-Tools (i.e. Xcelium, Genus, Innovus) and script languages (especially Python) and AI frameworks (i.e. TensorFlow, PyTorch
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