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: Investigate and design optimal computing and communication architectures for hardware acceleration of large-scale machine learning workloads Perform characterization and modeling of electronic and optical
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that multi-billion parameter models run on hardware hospitals can actually afford Your Profile - Completed university degree (Master or equivalent) in computer science, mathematics, physics, medical
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Max Planck Institute for Intelligent Systems, Tübingen, Tübingen | Bingen am Rhein, Rheinland Pfalz | Germany | about 5 hours ago
well as experience in computer vision and machine learning. Your tasks will be to: Develop and enhance capture systems, which include creating the hardware system and study design. Data collection using the developed
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, as a doctoral researcher, will: Explore energy–delay efficient unconventional computing architectures through both simulation and experimental prototyping Perform iterative hardware–algorithm co-design
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degree in computer science, mechatronics, or electrical engineering. Strong programming skills (C/C++, Python; hardware description languages such as HLS or VHDL are an advantage). Knowledge of computer
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assisted ISAC framework available at the TUM ACES Lab. ▪ Conducting real world experiments to analyze performance deviations between theoretical models, software simulations, and hardware behavior. ▪ Working
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practical research work, including lab experimentation, working with CAD models, and performing battery tests. You'll be part of a cross-disciplinary program aiming to design and validate next-generation
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programme Is the Job related to staff position within a Research Infrastructure? No Offer Description Your tasks: Developing optimization algorithms for massively parallel hardware architectures such as AI
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10 Dec 2025 Job Information Organisation/Company University of Siegen Research Field Computer science » Computer architecture Researcher Profile First Stage Researcher (R1) Positions PhD Positions
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. Responsibilities and tasks This PhD project aims to optimize the design of hybrid electrical–optical computing architectures: Investigate and design optimal computing and communication architectures for hardware