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of executive and senior leadership at Campus and JPL as part of ASIC's Annual Risk Assessment. Information from those meetings is used to develop the ASIC Annual Plan which is presented to and approved by
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travaux porteront sur la co-conception architecture / circuit / calibration, incluant le développement de cellules MDAC à temps continu, d'amplificateurs OTA large bande faible bruit, ainsi que de
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in the development of ASIC's annual risk assessment and Five-Year Compliance Assessment and Testing Plan. Assist in ASIC continual improvement efforts, developing new methodologies and documented
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. Working as part of SoC labs (https://soclabs.org/ ), you will design, develop and deliver workshops, lectures and online learning content in areas including digital electronic design, system‑on‑chip (SoC
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on-premises servers • Expertise in (or collaboration with experts in) ASIC design, high-bandwidth memory systems, ultra-speed data center networking, and related fields to push the boundaries of large-scale
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. Working as part of SoC labs (https://soclabs.org/), you will design, develop and deliver workshops, lectures and online learning content in areas including digital electronic design, system‑on‑chip (SoC
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, machine learning algorithms, and their hardware implementation considerations. Experience with ASIC design methodologies and open-source IC design and EDA tools. Prior experience in digital hardware design
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cutting-edge research in areas such as pattern recognition, automation science, complex systems, AI for Science, robotics, machine learning, computer vision, natural language processing, biometrics, medical
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FieldEngineeringEducation LevelPhD or equivalent Skills/Qualifications Who you are 15+ years of experience in digital ASIC design, 10+ years of experience with DFT insertion and ATPG Basic fluency with Verilog/VHDL to write
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/chiplets/interposer/wafer-scale), quantum, superconducting, machine learning, edge computing, and security/privacy in computer architecture. Digital Logic Design and VLSI – including ASIC/FPGA design for