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using state-of-the-art techniques. Develop bytecode to test and analyze VHDL for FPGAs and ensure hardware interfaces and controls meet the intended design. Who you are You have a BS in Computer
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of the following: C, C++, VHDL, Verilog, Python, C#. You’ve built, analyzed, debugged, and/or tested bare-metal systems and are familiar with a CMSIS/HAL/specific peripheral driver. You have experience
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Max Planck Institute for Extraterrestrial Physics, Garching | Garching an der Alz, Bayern | Germany | 3 months ago
function blocks. Design of test setups and development of peripheral circuits to test the target hardware for electronic modules and FPGA function blocks. Creation of test blocks in VHDL for verification
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on design of mixed-signal circuits. - Valuable Knowledge of comercial design tools like Cadence / Synopsys, ADS. - Competence in computer architectures and digital system design with HDLs (Verilog or VHDL
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infrastructure (e.g., OpenStack, OpenShift). Knowledge of sensor electronics, FPGA development (e.g., VHDL), and sensor electronics prototyping. Excellent written and oral communication skills. Motivated self
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acquisition for scientific user facilities. Ten or more years leading FPGA firmware development with AMD/Xilinx FPGAs in VHDL with the Vivado tool suite including demonstrated expertise in high-speed data
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++. Experience in RTL design and FPGA prototyping using VHDL/Verilog and/or HLS tools is highly desirable A research-oriented attitude along with a result-focused mindset. Ability to work in a collaborative
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knowledge and experience in VHDL Design and Integrated Circuits Design. The ability to apply and generate externally funded research projects is highly desirable. Administrative responsibilities
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hardware description languages (HDLs) such as Verilog or VHDL Strong understanding of digital design principles and embedded systems Proficiency in low-level programming languages such as C, Rust and RISC-V
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accelerator applications, especially storage ring lattice and orbit control. Proficient in RTL design (Verilog/SystemVerilog/VHDL), IP integration, simulation, timing closure, and FPGA deployment. Skilled in C