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++. Experience in RTL design and FPGA prototyping using VHDL/Verilog and/or HLS tools is highly desirable A research-oriented attitude along with a result-focused mindset. Ability to work in a collaborative
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field. Solid background in digital IC design and digital signal processing. Hands-on RTL design skills (SystemVerilog / Verilog / VHDL) plus scripting (Python / MATLAB / C/C++). Strong command of English
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