Sort by
Refine Your Search
-
Listed
-
Category
-
Country
-
Program
-
Field
-
School graduates over a thousand students who are ready to take on great ambitions and challenges. For more details, please view: https://www.ntu.edu.sg/eee We are looking for a Research Fellow to focus
-
School graduates over a thousand students who are ready to take on great ambitions and challenges. For more details, please view: https://www.ntu.edu.sg/eee We are looking for a Senior Research Fellow to
-
School graduates over a thousand students who are ready to take on great ambitions and challenges. For more details, please view: https://www.ntu.edu.sg/eee We are looking for a Research Associate to focus
-
- Experience with RTL languages (Verilog or VHDL), VHDL would be a plus - Proficiency with English language is highly recommended - Proficiency with French language would be a plus - Interest in technologies
-
the test engineering team on silicon characterization and validation Where to apply Website https://www.imec-int.com/en/work-at-imec/job-opportunities/dft-architect Requirements Research
-
-level programming and scripting languages, such as C/Assembly, TCL, VHDL/Verilog, SystemC, etc. Experience in applying for research and development funding. Proficient with Oscilloscopes, Logic Analyzers
-
architectures and digital system design with HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. Currently, pursuing a master's degree with specific content on electronic design, the
-
on design of mixed-signal circuits. - Valuable Knowledge of comercial design tools like Cadence / Synopsys. - Competence in computer architectures and digital system design with HDLs (Verilog or VHDL
-
HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. LanguagesENGLISHLevelExcellent LanguagesSPANISHLevelExcellent Additional Information Benefits The salary level is
-
Verilog description. Work Plan - Become familiar with the design flow in Workcraft - Become familiar with Signal Transition Graph (STG) design - Become familiar with specifying state machines in Verilog