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School graduates over a thousand students who are ready to take on great ambitions and challenges. For more details, please view: https://www.ntu.edu.sg/eee We are looking for a Research Fellow to focus
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School graduates over a thousand students who are ready to take on great ambitions and challenges. For more details, please view: https://www.ntu.edu.sg/eee We are looking for a Senior Research Fellow to
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School graduates over a thousand students who are ready to take on great ambitions and challenges. For more details, please view: https://www.ntu.edu.sg/eee We are looking for a Research Associate to focus
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(Scientific Research Fellow Status) in its current wording. https://www.fct.pt/wp-content/uploads/2026/01/RBi_Republicado_2025.pdf Regulations for Research Grants of the Foundation for Science and Technology in
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(Robot Simulation & Offline Programming), Microsoft Office Suite Programming Languages: Hardware-Level & Digital Design: Verilog, VHDL, Assembly. Data Science & Machine Learning: Python (Pandas, NumPy
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deployment enabling validation and demonstration of real-world applications. For more details, please view https://www.ntu.edu.sg/erian We are seeking a Research Engineer I to support our research and testing
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description language such VHDL or Verilog. Excellent communication (both writing and oral) and interpersonal skills. Can work independently or in a team. Willingness to take initiative. Applicants to provide
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Design Experience with GitHub software Experience with TAK/ATAK Experience with low-level programming and scripting languages, such as C/Assembly, TCL, VHDL/Verilog, SystemC, etc. Experience in applying
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Einstein Telescope collaborations, and with a network of industrial partners explores industrial and commercial applications of technologies developed in that context. — Astrocent (https://astrocent.edu.pl
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: OBJECTIVES | FUNCTIONS Automate the design of a register bank and the corresponding interface with I2C. The register bank as a variable number of addresses and it must be automatically designed in Verilog with