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measure power and delay. Required Qualifications Experience in Verilog, Cadence Virtuoso, synthesis, and RTL design. Desired Qualifications Excellent communication skills. Special Instructions to Applicants
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. Conocimientos en entornos de programación para control de convertidores: C/C++, Python, VHDL/Verilog para FPGAs o microcontroladores. Habilidad con software de diseño de PCBs como Altium Designer, KiCad, OrCAD o
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. Demonstrated programming experience in Python and C/C++ or Verilog, SystemVerilog. Excellent oral and written communication skills. Ability to work productively independently and collaboratively as part of a
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Python and C/C++ or Verilog, SystemVerilog. Excellent oral and written communication skills. Ability to work productively independently and collaboratively as part of a multidisciplinary team. Desired
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Engineering, or Computer Science, with relevant industrial or academic experience in digital hardware design, system modeling, and/or uArchitecture research. You are experienced in RTL design flows (Verilog
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hardware design (Verilog/VHDL), FPGA-based acceleration, etc. Experience with deep learning frameworks like PyTorch, Keras, or TensorFlow, and tools such as Jupyter Notebook, is expected. A strong foundation
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circuit using one or more of the software listed (Cadence; Fluent use of LT-Spice, Verilog-A, Python, ADS, ICCAP, etc.) Know how to perform circuit analysis and characterization Notice of Non-Discrimination