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, microarchitecture, and hardware/software co-design. Experience with RTL design (Verilog/SystemVerilog/VHDL) and integrating TLM with RTL for hybrid simulation environments is a plus. Familiarity with standard
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Python and/or MATLAB; familiarity with HDL (VHDL/Verilog) and FPGA design tools, e.g. Xilinx Vivado, Viti, is considered a plus Previous involvement in ESA, EU or other publicly funded research projects
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