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research on interactive verification of safety and security properties of challenging software systems. We offer full-time (37 hours/week) postdoc positions of 1-3 years. The starting date is December 1
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Job Description Real-time systems need to guarantee the timely execution of tasks. Furthermore, the whole system (processor, compiler, application software) needs to be analysable for the worst-case
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and exciting environment with plenty of opportunities for collaborations. In your role as a postdoc, you will focus on the formal verification techniques for process models, and the application
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Software Defined Vehicles (SDV). The primary objective is to expand, mature, and industrialize a novel European RISC-V automotive ecosystem that enables next-generation high-performance European automotive