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will be reported on the website where the offer is published. If applicable, indicate your request. Finally, the name of the person selected will be published on the same website where the offer is
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procedure is planned: interview, tests, etc ... Each phase of the selection process will be reported on the website where the offer is published. If applicable, indicate your request. Finally, the name of
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disciplinary or equivalent punishment that prevents access to public employment in the same terms in their own country. If an applicant, at any point during and before the completion of the recruitment process
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to be performed: the person hired must take care of: 1) Review of the data included in the lexical database 2) Maintenance and processing of the corpus of pre-university texts (EvAA) 3) Help in the design
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Considerable Requirements: - Postgraduate studies in quality management and/or auditing (0.3 points per degree, up to a maximum of 1 point). - Training in quality and safety certifications (0.10 points per
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reconstruction: 2 • Computer Science – 15 Auto Cad, Revit, Sketch up, GIS, i-Tree, NVivo, SPSS: 15 • Idioms – 10 English, Persian, Spanish, Arabic • Work Experience – 10 (1 point per year) • Interview (if deemed
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interpreting DESI data. Developing new tools and techniques for data processing and analysis. Exploring the large-scale distribution of galaxies and its implications for cosmology. This position is ideal for a
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16 Sep 2025 Job Information Organisation/Company Universidade de Vigo Department T14 Signal and Communications Theory Research Field Engineering » Other Researcher Profile First Stage Researcher (R1
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: - Postgraduate studies in quality management and/or auditing (0.3 points per degree, up to a maximum of 1 point). - Training in quality and safety certifications (0.10 points per certification or 0.20 points if in
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on design of mixed-signal circuits. - Valuable Knowledge of comercial design tools like Cadence / Synopsys, ADS. - Competence in computer architectures and digital system design with HDLs (Verilog or VHDL