19 algorithm-development-"The-University-of-Edinburgh"-"The-University-of-Edinburgh" positions at IMEC
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development. To integrate the image processing pipeline in a modular way, building on algorithms developed by your colleagues. To optimize performance and throughput and use software engineering best practices
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that develops advanced AI compute solutions involving AI models, algorithms, implementations, sensors and hardware for small scale edge up to large scale distributed and hybrid hardware architectures
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Description Join imec’s Platform Efficiency Team (PlatEff) as a Front-End-of-Line (FEOL) Integration Engineer, contributing to both technology development and technology transfer activities. This role offers
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need you as a Digital IC Design Engineer to be part of our multidisciplinary team to: Develop and implement RTL code that meets functional, performance, and area requirements based on design
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carrying out development plans. This includes defining the design of experiment, defining the in-line characterization strategy, following-up the processing in the imec pilot line, and analyzing and
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Device Engineer, contributing to technology development and technology transfer activities for both Front End Of Line (FEOL) and Back End Of Line (BEOL) process. This role offers high visibility with focus
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Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No Offer Description Join the Photonic device group to lead technically the development
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where you will be at the forefront of semiconductor innovation. The role involves collaboration with cross-functional teams to develop and implement novel process flows at imec’s 200mm and 300mm wafer
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Researcher, you will play a key role in developing next-generation quantum sensors based on photonic technologies, with applications spanning high-tech industries, space, and defense. Your work will focus
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characterization, resource management, system architecture, and microarchitecture. Develop performance (+power/TCO/emissions) models for future hardware at various levels of detail to identify bottlenecks and