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: Translate ML-based error-correction / DPD algorithms into hardware-friendly forms (model reduction, sparsity, quantization, fixed-point design). Design the architecture and RTL of a low-power accelerator that
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- Experience with RTL languages (Verilog or VHDL), VHDL would be a plus - Proficiency with English language is highly recommended - Proficiency with French language would be a plus - Interest in technologies
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: M.Sc. degree in Microelectronics, Electrical Engineering, or a closely related field. Strong background in analog, mixed-signal, and RF circuit design. Hands-on RTL design experience (SystemVerilog
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. Strong background in analog, mixed-signal, and RF circuit design. Hands-on RTL design experience (SystemVerilog, Verilog, or Verilog-AMS). Demonstrable creativity and originality in problem solving and