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: Investigate and design optimal computing and communication architectures for hardware acceleration of large-scale machine learning workloads Perform characterization and modeling of electronic and optical
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, as a doctoral researcher, will: Explore energy–delay efficient unconventional computing architectures through both simulation and experimental prototyping Perform iterative hardware–algorithm co-design
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-level layer implementations - extend hardware developments to use near-FPGA DDR and HBM memories - create functional demos using networks of interest (Yolo, Resnets, LLMs, ...) - create proof-of-concept
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of Nottingham. The Rolls-Royce UTC at the University of Nottingham is a leading research institution specializing in the development of soft and continuum robots for challenging environments (https
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huge signal-to-noise degradation due to significant path loss and blockage [3], which can partly be compensated using high-gain beamforming. Physical layer waveform design is also an important challenge
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these exiting domains. Topics include but are not limited to remote direct memory access, hardware offloading and acceleration, AI for networking and security, storage management, cryptography, and architecture
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, test, and demonstrate resilience strategies that enhance ISAC system robustness against various types of jamming. You will design, implement, and analyze ISAC resilience strategies using advanced
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of distributed MIMO, and/or coordinated multi-AP operation (under study in the Wi-Fi 8 standardisation workgroup), using Hardware Description Language on FPGA, based on the open-source openwifi project (https
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device in a way that makes good use of the available hardware resources. Your immediate leader will be the Head of the Computing Unit. About the project NICE is a center for research-driven innovation (i.e
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design next-generation computer architectures for running large AI models on embedded and edge systems under strict timing, energy, and memory constraints. You’ll explore hardware-aware optimization and co