149 structural-engineering-"https:"-"https:"-"https:"-"https:"-"https:" positions in Spain
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, ICFO is seeking an Engineer/Scientist with a background in optical engineering, material micro-nano-fabrication and PIC technologies, particularly in applied or industrial environments. Position Overview
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technologies for the monitoring, analysis, and prediction of structural integrity and fatigue life across diverse engineering applications. Where to apply Website https://www.uniovi.es/conocenos/rrhh
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23 Jan 2026 Job Information Organisation/Company Universitat Politècnica de Catalunya (UPC)- BarcelonaTECH Research Field Engineering » Industrial engineering Technology » Industrial technology
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23 Jan 2026 Job Information Organisation/Company Technical University of Cartagena Department Higher Technical School of Agricultural Engineering (ETSIA) Research Field Agricultural sciences
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Programme? Other EU programme Is the Job related to staff position within a Research Infrastructure? No Offer Description We are looking for a Postdoctoral Researcher in food technology to join the Food
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16 Jan 2026 Job Information Organisation/Company Universitat Politècnica de Catalunya (UPC)- BarcelonaTECH Research Field Engineering » Electronic engineering Engineering » Industrial engineering
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Field Engineering » Chemical engineering Researcher Profile First Stage Researcher (R1) Positions Master Positions Application Deadline 2 Feb 2026 - 00:00 (Europe/Madrid) Country Spain Type of Contract
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application development. We are seeking up to two Process Engineers or Research Scientists with hands-on experience in packaging and assembly of photonic integrated circuits (PICs). The selected candidates will
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ICFO is offering a Research Engineer position to a motivated and talented young scientist who wishes to start and develop their scientific career in a stimulating and collaborative environment
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an experienced engineer or research scientist specializing in the testing and characterization of photonic integrated circuits, with strong hands-on experience at die level, wafer level, and packaged level. The