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using state-of-the-art techniques. Develop bytecode to test and analyze VHDL for FPGAs and ensure hardware interfaces and controls meet the intended design. Who you are You have a BS with 8 years
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using state-of-the-art techniques. Develop bytecode to test and analyze VHDL for FPGAs and ensure hardware interfaces and controls meet the intended design. Who you are You have a BS with 8 years
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related field and a minimum of 5 years of relevant professional experience, or an MS and at least 4 years of relevant experience or a PhD. Demonstrated expertise and understanding of electrical engineering
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research community. Applicants should have a PhD in Electronics, Telecommunications or a closely related field. The application deadline is August 10, 2025, at 11.59 PM/23.59 (CET/CEST) Applicants
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Lab, D-ITET, ETH Zürich PhD student in Human-Computer Interaction: Adaptive Systems in Mixed Reality (UI + LLMs) 100%, Zurich, fixed-term 20.08.2025 | Sensing
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of DC/DC converter design and verification Experience of power converter control Experience of digital control and FPGA programming Experience in the use of GaN and SiC switches for power conversion