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Helmholtz-Zentrum Berlin für Materialien und Energie | Berlin, Berlin | Germany | about 2 months ago
28 Aug 2025 Job Information Organisation/Company Helmholtz-Zentrum Berlin für Materialien und Energie Research Field Physics Researcher Profile First Stage Researcher (R1) Country Germany
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Research Associate / PhD Student (m/f/x) (subject to personal qualification employees are remunerated according to salary group E 13 TV-L) starting earliest possible date. The position is limited to 3 years
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of Prof. Dr. Frank Cichos and Dr. Nico Scherf (Max Planck Institute for Human Cognition and Brain Sciences). The position is part of a collaborative project in the Center for Scalable Data Analytics and
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2 Oct 2025 Job Information Organisation/Company Forschungszentrum Jülich Research Field All Researcher Profile First Stage Researcher (R1) Country Germany Application Deadline 19 Jan 2038 - 03:14
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3 Oct 2025 Job Information Organisation/Company Forschungszentrum Jülich Research Field All Researcher Profile First Stage Researcher (R1) Country Germany Application Deadline 19 Jan 2038 - 03:14
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it is the working language of the lab. Desired skills Experience with analytical chemistry (LC/MS, GC/MS) and behavioral assays Experience with animal husbandry and colony maintenance. The Research
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Infrastructure? No Offer Description Work group: PGI-12 - Quantum Computing Analytics Area of research: Promotion Job description: Your Job: Your PhD project will be part of an interdisciplinary research project
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and is funded 90 percent by the German federal government and 10 percent by the State of Berlin. The RNA Biology Lab is looking for a highly motivated and enthusiastic PhD student (m/f/d) to join our
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- more information about the PhD program at the HZDR can be found here Salary and social benefits in accordance with the collective agreement for the public sector (TVöD-Bund) including 30 days of paid
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of embedded machine learning, neuromorphic hardware and deep learning accelerators. Want to get more information? Click here. What you will do Responsible for RTL design (VHDL, Verilog) of digital blocks and