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Field
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. - Hardware acceleration for the development of Artificial Intelligence & Machine Learning techniques using FPGA or other embedded hardware accelerators. - Management, configuration and optimisation
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implementation, including FPGA controlling Additional Information Selection process The selection process consists of an initial evaluation of the candidates' CV, motivation letter and specific merits
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of experience preferred, but fewer years may be considered if relevant. Proven skills in PCB design, FPGA development, and signal processing. Proactive, organized, and comfortable working in a multicultural
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, signal generators (including microwave), spectrum analyzers, soldering stations, and CAD software Experience with microcontrollers, FPGA programming, and LabVIEW Excellent communication skills. Ability
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of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and/or P&R. Knowledge of FPGA-development is a plus. Knowledge of low-power designs is a plus
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infrastructure (e.g., OpenStack, OpenShift). Knowledge of sensor electronics, FPGA development (e.g., VHDL), and sensor electronics prototyping. Excellent written and oral communication skills. Motivated self
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. (preferred) or M.Sc. in Electrical Engineering, Telecommunications Engineering, or a closely related field. SDR Expertise: Strong hands-on experience with SDRs (USRP, RFSoC, or equivalent). FPGA programming
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central to developing advanced safety control systems that protect people in complex, high-risk environments, while also leading software development projects that integrate PLCs, FPGAs, and EPICS into next
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PLCs, FPGAs, and EPICS into next-generation accelerator systems. Your work will help shape the future of safety engineering at Berkeley Lab and beyond, with opportunities to collaborate across DOE labs
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related to developing, securing, or using AI chips and workloads, from edge devices to data centers. Topics of interest include, but are not limited to, GPUs, FPGAs, custom accelerators, protecting model IP