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Field
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central to developing advanced safety control systems that protect people in complex, high-risk environments, while also leading software development projects that integrate PLCs, FPGAs, and EPICS into next
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implementation, including FPGA controlling Additional Information Selection process The selection process consists of an initial evaluation of the candidates' CV, motivation letter and specific merits
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PLCs, FPGAs, and EPICS into next-generation accelerator systems. Your work will help shape the future of safety engineering at Berkeley Lab and beyond, with opportunities to collaborate across DOE labs
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of experience preferred, but fewer years may be considered if relevant. Proven skills in PCB design, FPGA development, and signal processing. Proactive, organized, and comfortable working in a multicultural
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Communications protocols OSI stack UDP/TCP/IP Familiarity with wireless specifications such as cellular(4G/5G)/Wi-Fi (802.11) FPGA development Microcontroller and Digital Signal Processor (DSP) development MATLAB
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Reconfigurable/Spatial computing architectures, such as FPGAs, CGRAs, and AI accelerators, offer significant opportunities for improving performance and energy efficiency compared to traditional CPUs
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(e.g., hardware trojans, side-channel exposure). Co-develop testbenches for hardware simulations and chiplet-level threat modelling. Collaborate closely with FPGA and IC prototyping teams to deploy AI
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++ programming languages and data analysis techniques General knowledge of microelectronics and FPGAs (VHDL or Verilog) is desirable Knowledge in radiation physics and dosimetry Interdisciplinary collaboration
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/chiplets/interposer/wafer-scale), quantum, superconducting, machine learning, edge computing, and security/privacy in computer architecture. Digital Logic Design and VLSI – including ASIC/FPGA design for
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programming (including a C-to-Python library), and building a computing and networking infrastructure for a new laboratory, including experimental control software and FPGA programming. Position is expected