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Field
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into the co-design of ultra-low-power AI hardware architectures tailored for edge computing applications. The research aims to develop neuromorphic processors, FPGA/ASIC-based AI accelerators, and intelligent
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. Familiarity and understanding of microwave and RF measurement circuit elements and instruments Familiarity with Field Programmable Gate Array (FPGA) operation and coding Skills Needed: Knowledge, understanding
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/chiplets/interposer/wafer-scale), quantum, superconducting, machine learning, edge computing, and security/privacy in computer architecture. Digital Logic Design and VLSI – including ASIC/FPGA design for
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software and hardware (knowledge on working with FPGAs and ASICs will be preferred). Achievement of the expected progression within Post Doc and Senior Post Doc is transferable between the Irish HEI’s
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: Experience in real-time simulation hardware like Opal-RT and RTDS. Experience with software development. Experience with use of DSPs, FPGAs, advanced computing (e.g., GPUs, QPUs). Excellent written and oral
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preferred; Hands- on experience in one of the following areas and desire to cross the boundaries and learn new things Embedded software development for the FPGA / CPU SoC systems (for example, Zynq 7000, Zynq
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. The advertised position revolves around design and test of custom radio-frequency electronic circuits based on field-programmable gate arrays (FPGA, up to 20GHz) to drive high-speed electro-optic modulators, quasi
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project. The research will bridge both established and emerging technical expertise within the section, encompassing areas such as FPGA and neuromorphic computing, Edge AI, machine learning, power
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hardware design (Verilog/VHDL), FPGA-based acceleration, etc. Experience with deep learning frameworks like PyTorch, Keras, or TensorFlow, and tools such as Jupyter Notebook, is expected. A strong foundation
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/chiplets/interposer/wafer-scale), quantum, superconducting, machine learning, edge computing, and security/privacy in computer architecture. Digital Logic Design and VLSI – including ASIC/FPGA design for