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of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and/or P&R. Knowledge of FPGA-development is a plus. Knowledge of low-power designs is a plus
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board design or FPGA programming is a plus. Experience with automatic, semi-automatic probe-stations or manual probe measurement and notions on probe pad layouts and probecard design is a plus. You have
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can understand their limitations and take those into account in your design for test strategy. Experience with either PCB, demo board design or FPGA programming is a plus. Experience with automatic
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