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Field
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strategies for programming, modeling, and integrating reconfigurable/spatial architectures, such as FPGAs and ML accelerators, within heterogeneous ICT ecosystems. Reconfigurable and Spatial hardware, such as
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or Computer Engineering. 12 years of experience in digital or system architecture for SoC/FPGA/ASIC designs, with strong exposure to AI, networking, or HPC accelerators. Deep expertise in dataflow architectures
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LevelUndergraduate Skills/Qualifications - Conocimientos de programación y uso de sistemas basados en microprocesadores. - Conocimientos de diseño de circuitos digitales para sistemas reconfigurables basados en FPGA
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monitoring will also be integrated into this PhD. Thermal prediction models are currently implemented on a Field Programmable Gate Array (FPGA), while the thermal PI controller (which will be further developed
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experience dealing with custom hardware, FPGAs, and using/writing APIs to communicate with the hardware Like to live in the intersection of biology, hardware, and coding Ability to prioritize and conduct
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optics, ideally, knowledge of electronics, Python and FPGA (VHDL) programming, interest in working with experts on a cross-institute collaboration project, very good written and spoken English language
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Specific Integrated Circuits (ASIC), Processors (CPU, GPU, VPU and accelerators), Field Programmable Gate Arrays (FPGA) and System-on-Chips (SoCs), as well as Intellectual Property (IP) Core developments for
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of distributed MIMO, and/or coordinated multi-AP operation (under study in the Wi-Fi 8 standardisation workgroup), using Hardware Description Language on FPGA, based on the open-source openwifi project (https
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exposing hardware accelerators, such as GPUs and FPGAs, in a seamless and portable way. This includes designing execution logic and resource-scheduling strategies that make efficient use of available
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skills in designing advanced neural networks (including Vision Transformers, Graph Convolutional Networks, and Spiking Neural Networks), hardware implementation of algorithms for reconfigurable FPGA