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Job Title: Research Associate / Research Fellow in FPGA Systems Design (SPEAR Centre) Department/School: School of Computing, Engineering & Intelligent Systems Campus: Derry~Londonderry campus
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Role: Research Associate / Research Fellow in FPGA Systems Design Department: School of Computing, Engineering and Intelligent Systems Grade: Appointment at Research Associate level - Grade 6/7
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include the development and implementation of control algorithms on FPGA platforms, experimental testing using Hardware-in-the-Loop (HIL) setups, data analysis, and preparation of scientific publications
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strategies for programming, modeling, and integrating reconfigurable/spatial architectures, such as FPGAs and ML accelerators, within heterogeneous ICT ecosystems.Reconfigurable and Spatial hardware, such as
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topics. Candidates should have some experience working with FPGAs as well as an understanding of computer networks. Experience with both RTL and HLS design is favoured. The ideal candidate would have some
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physics (HEP) detectors, neuromorphic computing, FPGA/ASIC design, and machine learning for edge processing. The successful candidate will work with a multi-institutional and multi-disciplinary team
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National Institute for Research and Development in Microtechnologies - IMT Bucharest | Romania | 16 days ago
applications using FPGA technology. Romanian citizen or citizen of another European Union member state; Resident in Romania; Very good (written, spoken) knowledge of Romanian and English. Specific Requirements
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techniques enabling full duplex or simultaneous communication–sensing operation Implement the proposed techniques on the 6GSPACE Lab testbeds (SDR/FPGA/RFSoC based platforms and NTN channel emulators
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. During the project, these modules will be emulated by RF FPGA boards designed at the beginning of the project. The first objective of the project will therefore be to propose a very low cost wireless link
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synchronization techniques enabling full duplex or simultaneous communication-sensing operation Implement the proposed techniques on the 6GSPACE Lab testbeds (SDR/FPGA/RFSoC based platforms and NTN channel