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of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and/or P&R. Knowledge of FPGA-development is a plus. Knowledge of low-power designs is a plus
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, microarchitecture, and hardware/software co-design. Experience with RTL design (Verilog/SystemVerilog/VHDL) and integrating TLM with RTL for hybrid simulation environments is a plus. Familiarity with standard
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complete solutions provider that can manage the full product lifecycle – serving start-ups, SMEs and established OEMs as well as universities. Our highly experienced ASIC development team realizes over 600
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