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hardware design and verification (HDL: VHDL/Verilog, simulation tools). · Hands-on experience with FPGA prototyping or hardware/software co-design is highly desirable. · Good communication
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work within the ADAPTING PEPR project, funded by France 2030 and led by the ANR (French National Research Agency). Within this project, the ASIC team at IETR aims to develop a distributed platform for
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