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energy-efficient CMOS blocks implementing SSM-based LLMs. Prototype hardware blocks on FPGA and prepare for ASIC tape-out. Benchmark performance and comparison with transformer accelerators. Work with
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engineering a strong background in digital design, hardware description languages (e.g. Verilog, VHDL, SystemC), reconfigurable architectures (e.g. FPGA, CGRA) What we expect from you: above-average degree
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Requirements: excellent university degree (master or comparable) in computer engineering or electrical engineering a strong background in digital design, hardware description languages (e.g. Verilog, VHDL
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Reconfigurable/Spatial computing architectures, such as FPGAs, CGRAs, and AI accelerators, offer significant opportunities for improving performance and energy efficiency compared to traditional CPUs
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experience of ASICS and electronics Good language skills, in particular a good command of both written and spoken English. Desired qualifications: Experience with manufacturing and quality assurance systems
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intelligence. This PhD project will leverage the power of field-programmable gate arrays (FPGA) to deploy machine learning models on the edge with low latency and high energy efficiency. This added intelligence
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Experience with VLSI design (Cadence tools, Verilog/VHDL, SPICE) Knowledge of neural networks and neuromorphic systems is a strong advantage Good programming skills (e.g., Python, MATLAB) and interest in
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of distributed MIMO, and/or coordinated multi-AP operation (under study in the Wi-Fi 8 standardisation workgroup), using Hardware Description Language on FPGA, based on the open-source openwifi project (https