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Field
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hardware design (Verilog/VHDL), FPGA-based acceleration, etc. Experience with deep learning frameworks like PyTorch, Keras, or TensorFlow, and tools such as Jupyter Notebook, is expected. A strong foundation
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of using FPGA tools and provide them the necessary training to use the ASIC tools. The team at Cambridge consists of three investigators: Prof. Robert Mullins (PI), Prof. Timothy Jones and Dr Rika Antonova
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, Computer Science, Experimental Subatomic Physics, or related fields. Relevant research experience in firmware programming (e.g. with VHDL) and resources optimization for specific FPGA architectures
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topics. Candidates should have some experience working with FPGAs as well as an understanding of computer networks. Experience with both RTL and HLS design is favoured. The ideal candidate would have some
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multilayer PCB, FPGA programming, embedded systems, and preferably ASIC-design. Knowledge in Systems Engineering, particularly in Space and Defence is highly regarded. You will also demonstrate personal
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Stanford University / SLAC National Accelerator Laboratory | Menlo Park, California | United States | about 8 hours ago
-the-Standard-Model searches using radioisotopes implanted in superconducting cryogenic sensors Development of ASIC electronics for sensor readout in cryogenic environments Nuclear structure measurements of 0𝜈ββ
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emulation software for FPGA-based electronics. • Experience contributing to data taking of large experiments. Additional Information: Application Instructions Applications should include: • A curriculum
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, or FPGAs control platforms. To be successful at shortlisting stage, please ensure you clearly evidence in your application how you meet the essential and, where applicable, desirable criteria listed in
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implementing quality assurance and quality control (QA/QC) test Designing testbenches, and contributing to firmware programming for state-of-the-art FPGA architectures, primarily Intel FPGAs. Collaborating
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, such as GPUs and FPGAs, to offloading applications in a seamless and portable way. This includes implementing runtime logic and resource scheduling strategies that can leverage available hardware