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                energy-efficient CMOS blocks implementing SSM-based LLMs. Prototype hardware blocks on FPGA and prepare for ASIC tape-out. Benchmark performance and comparison with transformer accelerators. Work with 
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                intelligence. This PhD project will leverage the power of field-programmable gate arrays (FPGA) to deploy machine learning models on the edge with low latency and high energy efficiency. This added intelligence 
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                Experience with VLSI design (Cadence tools, Verilog/VHDL, SPICE) Knowledge of neural networks and neuromorphic systems is a strong advantage Good programming skills (e.g., Python, MATLAB) and interest in 
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