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to develop enterprise architecture and strategies; apply appropriate change management methodologies; prioritize and work under the pressure of multiple demands while meeting/exceeding deadlines; prioritize
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18 Dec 2025 Job Information Organisation/Company FAPESP - São Paulo Research Foundation Research Field Architecture Researcher Profile Established Researcher (R3) Country Brazil Application Deadline
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18 Dec 2025 Job Information Organisation/Company FAPESP - São Paulo Research Foundation Research Field Architecture Researcher Profile Established Researcher (R3) Country Brazil Application Deadline
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Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No Offer Description Development of a shared-control architecture for human–robot
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University of North Carolina at Charlotte | Charlotte, North Carolina | United States | about 21 hours ago
Position Information General Information Position Number 001410, 004026 Working Title Assistant Professor Classification Title 9-Mo Tenure-Track/ Tenured Faculty College Col of Arts & Architecture
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19 Dec 2025 Job Information Organisation/Company TH Köln - University of Applied Sciences Research Field Architecture Arts Anthropology Computer science History » Art history Other Researcher
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19 Dec 2025 Job Information Organisation/Company Politechnika Rzeszowska (The Rzeszow University of Technology) Research Field Architecture » Other Researcher Profile Recognised Researcher (R2
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on design of mixed-signal circuits. - Valuable Knowledge of comercial design tools like Cadence / Synopsys. - Competence in computer architectures and digital system design with HDLs (Verilog or VHDL
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Requirements - Background on design of mixed-signal circuits. - Valuable Knowledge of comercial design tools like Cadence / Synopsys, ADS. - Competence in computer architectures and digital system design with
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architecture, computer systems, or chip design. You could have insights in, among others, System-on-Chip (SoC) and chiplet designs, with an emphasis on energy-efficient processors; hardware-software co-design to