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for an Engineer for ASIC Development (f/m/d) The Position Design of analog and mixed-signal ASIC blocks in CMOS technology for innovative X-ray pixel detectors in collaboration with international partners
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of executive and senior leadership at Campus and JPL as part of ASIC's Annual Risk Assessment. Information from those meetings is used to develop the ASIC Annual Plan which is presented to and approved by
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radar and communication systems. focus primarily on security related topics. contribute to the design of radar ASIC architectures. lead and execute (funded) projects in the security domain. publish in
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travaux porteront sur la co-conception architecture / circuit / calibration, incluant le développement de cellules MDAC à temps continu, d'amplificateurs OTA large bande faible bruit, ainsi que de
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in the development of ASIC's annual risk assessment and Five-Year Compliance Assessment and Testing Plan. Assist in ASIC continual improvement efforts, developing new methodologies and documented
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. Working as part of SoC labs (https://soclabs.org/ ), you will design, develop and deliver workshops, lectures and online learning content in areas including digital electronic design, system‑on‑chip (SoC
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research expertise in RISC-V architecture, processor microarchitecture, and AI accelerators. Experience with ASIC design methodologies and open-source IC design and EDA tools. Proven experience in digital
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on-premises servers • Expertise in (or collaboration with experts in) ASIC design, high-bandwidth memory systems, ultra-speed data center networking, and related fields to push the boundaries of large-scale
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. Strong research expertise in RISC-V architecture, processor microarchitecture, and AI accelerators. Experience with ASIC design methodologies and open-source IC design and EDA tools. Proven experience in
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. Working as part of SoC labs (https://soclabs.org/), you will design, develop and deliver workshops, lectures and online learning content in areas including digital electronic design, system‑on‑chip (SoC